`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2020/10/26 23:17:22
// Design Name: 
// Module Name: mycpu_top
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////
`include "defines.vh"

module mycpu_top(
    input  logic            clk,
    input  logic            res,
    input  logic [ 5: 0]    int_i,
    output logic            timer_int_o,
    //cpu instr sram
    output logic            inst_sram_en     ,
    output logic [ 3: 0]    inst_sram_wen    ,
    output logic [31: 0]    inst_sram_addr   ,
    output logic [31: 0]    inst_sram_wdata  ,
    input  logic [31: 0]    inst_sram_rdata  ,
    //cpu data sram
    output logic            data_sram_en     ,
    output logic [ 3: 0]    data_sram_wen    ,
    output logic [31: 0]    data_sram_addr   ,
    output logic [31: 0]    data_sram_wdata  ,
    input  logic [31: 0]    data_sram_rdata  ,

    output logic [31: 0]    debug_wb_pc      ,
    output logic [ 3: 0]    debug_wb_rf_wen  ,
    output logic [ 4: 0]    debug_wb_rf_wnum ,
    output logic [31: 0]    debug_wb_rf_wdata
    );


    // ---> FETCH <---
    logic [31: 0]           pc_next1_f;
    logic [31: 0]           pc_next2_f;
    logic [31: 0]           pc_f;
    logic [31: 0]           pc_plus4_f;
    logic [31: 0]           pc_read_f;
    logic                   stall_f;
    logic [`EXCS_BUS]       excs_f;
    logic                   flush_f;


    // ---> DECODE <---
    logic [31: 0]           pc_d;
    logic [31: 0]           instr_d;
    logic [31: 0]           pc_plus4_d;
    logic [31: 0]           compa_src_0_d;
    logic [31: 0]           compa_src_1_d;
    logic                   memtoreg_d;
    logic                   memwrite_d;
    logic                   branch_d;
    logic                   alusrc_d;
    logic [ 1: 0]           regdst_d;
    logic                   regwrite_d;
    logic                   jump_d;
    logic [ 1: 0]           ext_d;
    logic                   mduen_d;
    logic                   pcsrc_d;
    logic [31: 0]           pc_branch_d;
    logic [ 3: 0]           store_sel_d;
    logic [ 3: 0]           load_type_d;
    logic [ 3: 0]           branch_type_d;
    logic                   res_src_d;
    logic                   pcsrc2_d;
    logic [ 4: 0]           alucontrol_d;
    logic [31: 0]           read_rs_d;
    logic [31: 0]           read_rt_d;
    logic [31: 0]           read_rt2_d;
    logic [31: 0]           read_rd_d;
    logic [31: 0]           data_32bits_d;
    logic                   stall_d;
    logic                   compa_res_d;
    logic                   forward_a_d;
    logic                   forward_b_d;
    logic [`EXCS_BUS]       excs_d_i;
    logic [`EXCS_BUS]       excs_d_o;
    logic                   flush_d;

    // ---> EXECUTION <---
    logic [31: 0]           pc_e;
    logic                   memtoreg_e;
    logic                   memwrite_e;
    logic                   alusrc_e;
    logic [ 1: 0]           regdst_e;
    logic                   regwrite1_e;
    logic                   regwrite2_e; 
    logic                   mduen_e;
    logic [ 4: 0]           alucontrol_e;
    logic [31: 0]           read_rs_e;
    logic [31: 0]           read_rt_e;
    logic [31: 0]           read_rd_e;
    logic [ 4: 0]           rs_e;
    logic [ 4: 0]           rt_e;
    logic [ 4: 0]           rd_e;
    logic [ 4: 0]           sa_e;
    logic [31: 0]           data_32bits_e;
    logic [ 4: 0]           write_reg_e;
    logic [ 1: 0]           hilowrite_e;
    logic [63: 0]           hilo_o_e;
    logic                   cp0_we_e;
    logic [31: 0]           cp0_wdata_e;
    logic [ 7: 0]           cp0_wadr_e;
    logic [ 7: 0]           cp0_reg_adr_i_e;
    logic [ 7: 0]           cp0_reg_adr_o_e;
    logic [31: 0]           cp0_reg_data_i_e;
    logic                   cp0_reg_data_src_e;
    logic [ 2: 0]           cp0_sel_e;
    logic [ 3: 0]           store_sel_e;
    logic [ 3: 0]           load_type_e;
    logic                   res_src_e;
    logic                   stall_e;
    logic                   flush_e;
    logic [ 1: 0]           forward_a_e;
    logic [ 1: 0]           forward_b_e;    
    logic [31: 0]           alu_src_b1_e;
    logic [31: 0]           alu_src_b2_e;
    logic [31: 0]           alu_src_a_e;
    logic [31: 0]           alu_res_e;
    logic [ 1: 0]           hi_src_e;
    logic [ 1: 0]           lo_src_e;
    logic [31: 0]           hi_i_e;
    logic [31: 0]           lo_i_e;
    logic                   stallreq_alu_e;
    logic [`EXCS_BUS]       excs_e_i;
    logic [`EXCS_BUS]       excs_e_o;
        
    // ---> MEM <---
    logic [31: 0]           pc_m;
    logic                   memtoreg_m;
    logic                   memwrite_m;
    logic                   regwrite_m;
    logic [31: 0]           alu_res_m;
    logic [31: 0]           read_rt_m;
    logic [ 4: 0]           write_reg_m;
    logic [31: 0]           read_data_m;
    logic [ 1: 0]           hilowrite_m;
    logic [63: 0]           hilo_o_m;

    logic                   cp0_we_m;
    logic [31: 0]           cp0_wdata_m;
    logic [ 7: 0]           cp0_wadr_m;
    logic [31: 0]           cp0_rdata_m;
    logic [ 3: 0]           store_sel_m;
    logic [ 3: 0]           load_type_m;
    logic                   res_src_m;
    logic [31: 0]           res_m;
    logic                   flush_m;
    logic [`EXCS_BUS]       excs_m_i;
    logic [`EXCS_BUS]       excs_m_o;
    logic [31: 0]           flush_pc_m;

    // ---> WRITEBACK <---
    logic [31: 0]           pc_w;
    logic                   memtoreg_w;
    logic                   regwrite_w;
    logic [31: 0]           res_w;
    logic [31: 0]           read_data_w;
    logic [ 4: 0]           write_reg_w;
    logic [31: 0]           result_w;
    logic [ 1: 0]           hilowrite_w;
    logic [63: 0]           hilo_o_w;
    logic [31: 0]           hi_hilo_alu_w;   //from hilo to alu
    logic [31: 0]           lo_hilo_alu_w;
    logic                   flush_w;
    
    // >------<

    assign debug_wb_pc          = pc_w;
    assign debug_wb_rf_wen      = {4{regwrite_w}};
    assign debug_wb_rf_wdata    = result_w;
    assign debug_wb_rf_wnum     = write_reg_w;
    assign pcsrc_d              = branch_d & compa_res_d;
    assign cp0_reg_adr_i_e      = {rd_e, cp0_sel_e};

    logic [31: 0] inst_paddr;
    logic [31: 0] data_paddr;
 
    mmu mmu
    (
        .inst_vaddr     (pc_f                   ),
        .inst_paddr     (inst_paddr             ),
        .data_vaddr     (alu_res_m              ),
        .data_paddr     (data_paddr             )
    );
    
    // ---> FETCH <--- 

    mux3 mux3_pc_next1_f
    (   
        .s              ({jump_d,pcsrc_d}       ),
        .src_0          (pc_plus4_f             ),
        .src_1          (pc_branch_d            ),
        .src_2          ({pc_plus4_d [31:28], 
                          instr_d    [25: 0], 
                          2'b00}                ),
        .res            (pc_next1_f             )
    );

    mux2 mux2_pc_next2_f
    (
        .s              (pcsrc2_d               ),
        .src_0          (pc_next1_f             ),
        .src_1          (compa_src_0_d          ),
        .res            (pc_next2_f             )
    );

    pc_reg pc_reg
    (   
        .clk            (clk                    ),
        .res            (res                    ),
        .en             (~stall_f               ),
        .clr            (flush_f                ),
        .flush_pc       (flush_pc_m             ),
        .pc_next        (pc_next2_f             ),
        .pc             (pc_f                   ),
        .excs           (excs_f                 )
    );

    alu_pc alu_pc
    (   
        .pc             (pc_f                   ),
        .pc_plus4       (pc_plus4_f             )
    );

    instr_mem instr_mem
    (
        .pc_adr_i       (inst_paddr             ),
        .pc_read_i      (inst_sram_rdata        ),
        .en             (inst_sram_en           ),
        .we             (inst_sram_wen          ),
        .pc_adr_o       (inst_sram_addr         ),
        .pc_read_o      (pc_read_f              ),
        .pc_write       (inst_sram_wdata        )
    );

    F_D f_d
    (
        .clk            (clk                    ),
        .res            (res                    ),
        .clr            (flush_d                ),
        .en             (~stall_d               ),
        .pc_f           (pc_f                   ),
        .pc_read_f      (pc_read_f              ),
        .pc_plus4_f     (pc_plus4_f             ),
        .excs_f         (excs_f                 ),
        .pc_d           (pc_d                   ),
        .instr_d        (instr_d                ),
        .pc_plus4_d     (pc_plus4_d             ),
        .excs_d         (excs_d_i               )
    );

    // ---> DECODE <---
    logic next_is_slot_d;
    logic is_slot_alu_contr;
    logic inslot_d;
    control_unit control_unit
    (   
        .opcode1        (instr_d [31:26]        ),
        .opcode2        (instr_d [25:21]        ),
        .opcode3        (instr_d [10: 6]        ),
        .opcode4        (instr_d [20:16]        ),
        .funct          (instr_d [ 5: 0]        ),
        .excs_i         (excs_d_i               ),

        .memtoreg       (memtoreg_d             ),
        .memwrite       (memwrite_d             ),
        .branch         (branch_d               ),
        .alusrc         (alusrc_d               ),
        .regdst         (regdst_d               ),
        .regwrite       (regwrite_d             ),
        .jump           (jump_d                 ),
        .ext            (ext_d                  ),
        .alucontrol     (alucontrol_d           ),
        .mduen          (mduen_d                ),
        .store_sel      (store_sel_d            ),
        .load_type      (load_type_d            ),
        .branch_type    (branch_type_d          ),
        .res_src        (res_src_d              ),
        .pcsrc2         (pcsrc2_d               ),
        .excs_o         (excs_d_o               ),
        .next_is_slot   (next_is_slot_d         ),
        .is_slot_i      (is_slot_alu_contr      ),
        .inslot         (inslot_d               )
    );
    
    mux2 mux2_compa_src_0_d
    (   
        .s              (forward_a_d            ),
        .src_0          (read_rs_d              ),
        .src_1          (res_m                  ),
        .res            (compa_src_0_d          )
    );

    mux2 mux2_compa_src_1_d
    (  
        .s              (forward_b_d            ),
        .src_0          (read_rt_d              ),
        .src_1          (res_m                  ),
        .res            (compa_src_1_d          )
    );

    compa compa
    (   
        .branch_type    (branch_type_d          ),
        .src_0          (compa_src_0_d          ),
        .src_1          (compa_src_1_d          ),
        .res            (compa_res_d            )
    );

    //so that store_inst can read true rt value
    mux2 mux2_rt2_d  
    (                   
        .s              (forward_b_d&memwrite_d ),
        .src_0          (read_rt_d              ),
        .src_1          (alu_res_m              ),
        .res            (read_rt2_d             )
    );

    regfile regfile
    (   
        .clk            (clk                    ),
        .we             (regwrite_w             ),
        .radr1          (instr_d [25:21]        ), //rs
        .radr2          (instr_d [20:16]        ), //rt
        .radr3          (instr_d [15:11]        ), //rd

        .radr4          (write_reg_w            ),
        .write_data     (result_w               ),
        .read_rs        (read_rs_d              ),
        .read_rt        (read_rt_d              ),
        .read_rd        (read_rd_d              )
    );

    sign_extend sign_extend
    (   
        .data_16bits    (instr_d [15: 0]        ),
        .ext            (ext_d                  ),
        .data_32bits    (data_32bits_d          )
    );

    alu_pcbranch alu_pcbranch
    (   
        .pc_plus4       (pc_plus4_d             ),
        .offset         (data_32bits_d          ),
        .pc_branch      (pc_branch_d            )
    );

    logic next_is_slot_e;
    logic inslot_e;
    D_E d_e
    (   
        .clk            (clk                    ),
        .res            (res                    ),
        .en             (~stall_e               ),
        .clr            (flush_e                ),

        .pc_d           (pc_d                   ),
        .memtoreg_d     (memtoreg_d             ),
        .memwrite_d     (memwrite_d             ),
        .alusrc_d       (alusrc_d               ),
        .regdst_d       (regdst_d               ),
        .regwrite_d     (regwrite_d             ),
        .alucontrol_d   (alucontrol_d           ),
        .read_rs_d      (read_rs_d              ),
        .read_rt_d      (read_rt2_d             ),
        .read_rd_d      (read_rd_d              ),
        .rs_d           (instr_d [25:21]        ),
        .rt_d           (instr_d [20:16]        ),
        .rd_d           (instr_d [15:11]        ),
        .sa_d           (instr_d [10: 6]        ),
        .data_32bits_d  (data_32bits_d          ),
        .mduen_d        (mduen_d                ),
        .cp0_sel_d      (instr_d [ 2: 0]        ),
        .store_sel_d    (store_sel_d            ),
        .load_type_d    (load_type_d            ),
        .res_src_d      (res_src_d              ),
        .excs_d         (excs_d_o               ),
        .next_is_slot_d (next_is_slot_d         ),
        .inslot_d       (inslot_d               ),
        
        .pc_e           (pc_e                   ),
        .memtoreg_e     (memtoreg_e             ),
        .memwrite_e     (memwrite_e             ),
        .alusrc_e       (alusrc_e               ),
        .regdst_e       (regdst_e               ),
        .regwrite_e     (regwrite1_e            ),
        .alucontrol_e   (alucontrol_e           ),
        .read_rs_e      (read_rs_e              ),
        .read_rt_e      (read_rt_e              ),
        .read_rd_e      (read_rd_e              ),
        .rs_e           (rs_e                   ),
        .rt_e           (rt_e                   ),
        .rd_e           (rd_e                   ),
        .sa_e           (sa_e                   ),
        .data_32bits_e  (data_32bits_e          ),
        .mduen_e        (mduen_e                ),
        .cp0_sel_e      (cp0_sel_e              ),
        .store_sel_e    (store_sel_e            ),
        .load_type_e    (load_type_e            ),
        .res_src_e      (res_src_e              ),
        .excs_e         (excs_e_i               ),
        .next_is_slot_e (next_is_slot_e         ),
        .inslot_e       (inslot_e               )
    );


    // ---> EXECUTION <---

    mux3 #(5) mux2_write_reg_e
    (   
        .s              (regdst_e               ),
        .src_0          (rt_e                   ),
        .src_1          (rd_e                   ),
        .src_2          (5'b11111               ),
        .res            (write_reg_e            )
    );

    mux3 mux3_alu_src_a_e
    (   
        .s              (forward_a_e            ),
        .src_0          (read_rs_e              ),
        .src_1          (result_w               ),
        .src_2          (res_m                  ),
        .res            (alu_src_a_e            )
    );

    mux3 mux3_alu_src_b1_e
    (   
        .s              (forward_b_e            ),
        .src_0          (read_rt_e              ),
        .src_1          (result_w               ),
        .src_2          (res_m                  ),
        .res            (alu_src_b1_e           )
    );

    mux2 mux2__alu_src_b2_e
    (   
        .s              (alusrc_e               ),
        .src_0          (alu_src_b1_e           ),
        .src_1          (data_32bits_e          ),
        .res            (alu_src_b2_e           )
    );

    mux3 mux3_hi_i_e
    (   .s              (hi_src_e               ),
        .src_0          (hi_hilo_alu_w          ),
        .src_1          (hilo_o_m [63:32]       ),
        .src_2          (hilo_o_w [63:32]       ),
        .res            (hi_i_e                 )
    );

    mux3 mux3_lo_i_e
    (   .s              (lo_src_e               ),
        .src_0          (lo_hilo_alu_w          ),
        .src_1          (hilo_o_m [31: 0]       ),
        .src_2          (hilo_o_w [31: 0]       ),
        .res            (lo_i_e                 )
    );

    mux2 mux2_cp0_reg_data_i_e
    (
        .s              (cp0_reg_data_src_e     ),
        .src_0          (cp0_rdata_m            ),
        .src_1          (cp0_wdata_m            ),
        .res            (cp0_reg_data_i_e       )
    ); 
    
    logic is_slot_e;
    alu alu
    (   
        .clk            (clk                    ),
        .alu_control    (alucontrol_e           ),
        .src_a          (alu_src_a_e            ),
        .src_b          (alu_src_b2_e           ),
        .src_c          (sa_e                   ),
        .hi_i           (hi_i_e                 ),
        .lo_i           (lo_i_e                 ),
        .regwrite_i     (regwrite1_e            ),
        .regwrite_o     (regwrite2_e            ), //regwrite1_e after exception
        .hilowrite_e    (hilowrite_e            ),
        .alu_res        (alu_res_e              ),
        .stall          (stall_e                ),
        .stallreq       (stallreq_alu_e         ),
        .mduen          (mduen_e                ),
        .hilo_o         (hilo_o_e               ),
        .cp0_reg_data_i (cp0_reg_data_i_e       ),
        .cp0_reg_adr    (cp0_reg_adr_i_e        ),
        .cp0_radr_o     (cp0_reg_adr_o_e        ),
        .cp0_we_o       (cp0_we_e               ),
        .cp0_data_o     (cp0_wdata_e            ),
        .cp0_wadr_o     (cp0_wadr_e             ),
        .excs_i         (excs_e_i               ),
        .excs_o         (excs_e_o               ),
        .next_is_slot_i (next_is_slot_e         ),
        .is_slot_o      (is_slot_alu_contr      )
    );

    logic inslot_m;
    E_M e_m
    (   
        .clk            (clk                    ),
        .res            (res                    ),
        .clr            (flush_m                ),

        .pc_e           (pc_e                   ),
        .memtoreg_e     (memtoreg_e             ),
        .memwrite_e     (memwrite_e             ),
        .regwrite_e     (regwrite2_e            ),
        .alu_res_e      (alu_res_e              ),
        .write_data_e   (read_rt_e              ),
        .write_reg_e    (write_reg_e            ),
        .hilowrite_e    (hilowrite_e            ),
        .hilo_o_e       (hilo_o_e               ),
        .cp0_data_e     (cp0_wdata_e            ),
        .cp0_we_e       (cp0_we_e               ),
        .cp0_wadr_e     (cp0_wadr_e             ),
        .store_sel_e    (store_sel_e            ),
        .load_type_e    (load_type_e            ),
        .res_src_e      (res_src_e              ),
        .excs_e         (excs_e_o               ),
        .inslot_e       (inslot_e               ),
        
        .pc_m           (pc_m                   ),
        .memtoreg_m     (memtoreg_m             ),
        .memwrite_m     (memwrite_m             ),
        .regwrite_m     (regwrite_m             ),
        .alu_res_m      (alu_res_m              ),
        .write_data_m   (read_rt_m              ),
        .write_reg_m    (write_reg_m            ),
        .hilowrite_m    (hilowrite_m            ),
        .hilo_o_m       (hilo_o_m               ),
        .cp0_data_m     (cp0_wdata_m            ),
        .cp0_we_m       (cp0_we_m               ),
        .cp0_wadr_m     (cp0_wadr_m             ),
        .store_sel_m    (store_sel_m            ),
        .load_type_m    (load_type_m            ),
        .res_src_m      (res_src_m              ),
        .excs_m         (excs_m_i               ),
        .inslot_m       (inslot_m               )
    );

    // ---> MEM <---
    
    mux2 mux2_res_M
    (
        .s              (res_src_m              ),
        .src_0          (alu_res_m              ),
        .src_1          (pc_m + 8               ),
        .res            (res_m                  )
    );

    data_mem data_mem
    (
        .store_sel      (store_sel_m            ),
        .load_type      (load_type_m            ),

        .we_i           (memwrite_m             ),
        .adr_i          (data_paddr             ),
        .write_data_i   (read_rt_m              ),
        .read_data_i    (data_sram_rdata        ),

        .en             (data_sram_en           ),
        .we_o           (data_sram_wen          ),   //---> data_ram
        .adr_o          (data_sram_addr         ),   //---> data_ram
        .write_data_o   (data_sram_wdata        ),   //---> data_ram
        .read_data_o    (read_data_m            ),   //---> datapath
        .excs_i         (excs_m_i               ),
        .excs_o         (excs_m_o               )
    );

    logic [31: 0]           badadr_o_m;
    logic                   exc_flag_m;
    logic [`EXCT_BUS]       exc_type_m;
    exception exception
    (
        .pc_i           (pc_m                   ),
        .mem_adr_i      (alu_res_m              ),
        .badadr_o       (badadr_o_m             ),
        .excs_i         (excs_m_o               ),
        .exc_intr_i     (exc_intr_m             ),  
        .exc_flag       (exc_flag_m             ),
        .exc_type       (exc_type_m             ),
        .flush_pc       (flush_pc_m             ),
        .epc_i          (epc_cp0_exc_m          )
    );

    logic [31: 0] count_cp0_exc_m;
    logic [31: 0] status_cp0_exc_m;
    logic [31: 0] cause_cp0_exc_m;
    logic [31: 0] epc_cp0_exc_m;
    logic         exc_intr_m;
    logic exc_save_m;
    assign exc_save_m = memwrite_m;
    cp0 cp0
    (
        .clk            (clk                    ),
        .res            (res                    ),
        .int_i          (int_i                  ),
        .adr            (cp0_reg_adr_o_e        ),
        .wdata          (cp0_wdata_m            ),
        .we             (cp0_we_m               ),
        .wadr           (cp0_wadr_m             ),
        .data           (cp0_rdata_m            ),
        .inslot         (inslot_m               ),
        .pc_i           (pc_m                   ),
        .badadr         (badadr_o_m             ),
        .exc_save       (exc_save_m             ),
        .exc_flag       (exc_flag_m             ),
        .exc_type       (exc_type_m             ),
        .exc_intr_o     (exc_intr_m             ),
        .count_o        (count_cp0_exc_m        ),
        .status_o       (status_cp0_exc_m       ),
        .cause_o        (cause_cp0_exc_m        ),
        .epc_o          (epc_cp0_exc_m          ),
        .timer_int_o    (timer_int_o            )
    );

    M_W m_w
    (   
        .clk            (clk                    ),
        .res            (res                    ),
        .clr            (flush_w                ),
        
        .pc_m           (pc_m                   ),
        .memtoreg_m     (memtoreg_m             ),
        .regwrite_m     (regwrite_m             ),
        .res_m          (res_m                  ),
        .read_data_m    (read_data_m            ),
        .write_reg_m    (write_reg_m            ),
        .hilowrite_m    (hilowrite_m            ),
        .hilo_o_m       (hilo_o_m               ),

        .pc_w           (pc_w                   ),
        .memtoreg_w     (memtoreg_w             ),
        .regwrite_w     (regwrite_w             ),
        .res_w          (res_w                  ),
        .read_data_w    (read_data_w            ),
        .write_reg_w    (write_reg_w            ),
        .hilowrite_w    (hilowrite_w            ),
        .hilo_o_w       (hilo_o_w               )
    );

    // ---> WRITEBACK <---

    mux2 mux2_result_w
    (   
        .s              (memtoreg_w             ),
        .src_0          (res_w                  ),
        .src_1          (read_data_w            ),
        .res            (result_w               )
    );


    hilo hilo
    (   
        .clk            (clk                    ),
        .res            (res                    ),
        .we             (hilowrite_w            ),
        .hilo_i         (hilo_o_w               ),
        .hi_o           (hi_hilo_alu_w          ),
        .lo_o           (lo_hilo_alu_w          )
    );

    hazard_unit hazard_unit
    (   
        .memwrite_d     (memwrite_d             ),
        .branch_d       (branch_d               ),
        .rs_d           (instr_d [25:21]        ),
        .rt_d           (instr_d [20:16]        ),
        .rd_d           (instr_d [15:11]        ),
        .alucontrol_d   (alucontrol_d           ),
        .rs_e           (rs_e                   ),
        .rt_e           (rt_e                   ),
        .rd_e           (rd_e                   ),
        .pcsrc2_d       (pcsrc2_d               ),
        .write_reg_e    (write_reg_e            ),
        .memtoreg_e     (memtoreg_e             ),
        .regwrite2_e    (regwrite2_e            ),
        .memtoreg_m     (memtoreg_m             ),
        .regwrite_m     (regwrite_m             ),
        .write_reg_m    (write_reg_m            ),
        .write_reg_w    (write_reg_w            ),
        .regwrite_w     (regwrite_w             ),              
        .alucontrol_e   (alucontrol_e           ),
        .hilowrite_m    (hilowrite_m            ),
        .hilowrite_w    (hilowrite_w            ),
        .stallreq_alu_e (stallreq_alu_e         ),
        .hi_src_e       (hi_src_e               ),
        .lo_src_e       (lo_src_e               ),
        .forward_a_e    (forward_a_e            ),
        .forward_b_e    (forward_b_e            ),
        .forward_a_d    (forward_a_d            ),
        .forward_b_d    (forward_b_d            ),
        .stall_f        (stall_f                ),
        .stall_d        (stall_d                ),
        .stall_e        (stall_e                ),
        .flush_f        (flush_f                ),
        .flush_d        (flush_d                ),
        .flush_e        (flush_e                ),
        .flush_m        (flush_m                ),
        .flush_w        (flush_w                ),
        .cp0_we_m       (cp0_we_m               ),
        .exc_flag_i     (exc_flag_m             ),
        .cp0_radr_e     (cp0_reg_adr_o_e        ),
        .cp0_wadr_m     (cp0_wadr_m             ),
        .cp0_reg_data_src_e (cp0_reg_data_src_e )
    );


endmodule
